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NAND Memory: Beginning of the 3D era – Competition Builds

August 15th, 2013

NAND memory 3D EraSamsung has recently announced that it is going to begin mass production of 3D vertical NAND (V NAND), which is based on the vertical arrangement of charge-trapped cells rather than conventional floating gate non-volatile cells used in 2D NAND. It appears that initial production at line No.16 is for sampling purpose. We believe that Samsung will use 3xnm lithography and stack up to 24 layers to produce the 128Gb NAND.

In 2D terms, this product would have a similar degree of integration as 16nm. Given the initial production stage, we do not expect a meaningful improvement in cost competitiveness – for 10 k wafers/month of capacity, KRW300bn is required for 2D and KRW500bn for 3D, in our view. But, due to the vertical stacking of memory cells, processing speed is 2x that of regular 2xnm. Due to larger memory cell, V NAND technology offers 2-10x the reliability of current generation and 2x the write performance. Thus, we expect the initial shipment to be used for server SSD, which requires high performance.

Considering that SK Hynix is likely to expand 20 k wafers/month of NAND capacity in 2013F and Micron may convert 40-60 k wafers/month of DRAM facility to NAND, we expect global NAND capacity to increase by 6-8% y-y in 2013F. With that said, However, we believe it would be difficult for NAND players to make aggressive investments into 2D technology in the face of 3D era. We also expect Toshiba to be ready for the mass production of V NAND and SK Hynix to be able to set up a pilot line in line No.12 (c.60 k wafers/month of free capacity). Overall, we expect NAND capacity to increase but the level is within our original expectation.

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